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UTC CD4541
PROGRAMMABLE TIMER
DESCRIPTION
The UTC CD4541 programmable timer comprise a 16-stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, output control logic, and a special power-on reset circuit. The counter divides the oscillator frequency by any of 4 digitally controlled division ratios.
CMOS IC
SOP-14
FEATURES
*Operates at 2n frequency divider or as single transition timer *Increments on positive edge clock transitions *Wide supply voltage range: 3.0V ~ 15V *Built-in low power RC oscillator *Oscillator frequency range ~ DC to 100 kHz *External clock applied to Pin 3 can be used instead of oscillator 8 10 13 16 *Available division ratios 2 , 2 , 2 , or 2 *High noise immunity: 0.45 VDD (typ.) *Master reset totally independent of automatic reset operation *Automatic reset initializes all counters when power turns on *Q/Q select provides output logic level flexibility *High output drive min. one TTL load *Maximum input leakage 1 A at 15V over full temperature range
DIP-14
*Pb-free plating product number: CD4541L
PIN CONFIGURATION
Rtc Ctc Rs N.C. AR MR Vss
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VDD B A N.C. MODE Q/Q SELECT Q
UTC UNISONIC TECHNOLOGIES
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CO., LTD.
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UTC CD4541
TRUTH TABLE
PIN 5 6 9 10 STATE 0 Auto Reset Operating Timer Operational Output Initially Low after Reset Single Cycle Mode 1 Auto Reset Disabled Master Reset On Output Initially High after Reset Recycle Mode
CMOS IC
DIVISION RATIO TABLE
A 0 0 1 1 B 0 1 0 1 Number of Counter Stages n 13 10 8 16 Count 2n 8192 1024 256 65536
BLOCK DIAGRAM
A 12 B 13 1 OF 3 MUX Rtc 1 Ctc 2 Rs 3 OSC RESET 8-STAGE 8 C COUNTER 2 RESET 210 213 216 B-STAGE C COUNTER RESET
8Q
AUTO RESET 5
POWER-ON RESET
6 10 MODE
VDD=Pin 14 Vss=Pin 7
MASTER RESET
9 Q/Q SELECT
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ABSOLUTE MAXIMUM RATINGS
(Note 1, 2) PARAMETER Supply Voltage Input Voltage DIP-14 SOP-14 Lead Temperature (soldering, 10 seconds) Storage Temperature Range Power Dissipation SYMBOL VDD VIN PD TL Tstg RATINGS -0.5 ~ +18 -0.5 ~ VDD+0.5 700 500 260 -65 ~ +150
CMOS IC
UNIT V V mW
RECOMMENDED OPERATING CONDITIONS
(Note 2) PARAMETER SYMBOL RATINGS UNIT Supply Voltage VDD 3 ~ 15 V Input Voltage VIN 0 ~ VDD V Operating Temperature Range Topr -40 ~ +85 Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Note 2: VSS=0V unless otherwise specified.
DC ELECTRICAL CHARACTERISTICS
(Note 2, Ta=25 , unless otherwise noted.) TEST CONDITIONS VDD=5V, VIN=VDD or Vss VDD=10V, VIN=VDD or Vss Quiescent Device Current IDD VDD=15V, VIN=VDD or Vss VDD=5V VDD=10V, I IO I<1 A LOW Level Output Voltage VOL VDD=15V VDD=5V VDD=10V, I IO I<1 A HIGH Level Output Voltage VOH VDD=15V VDD=5V, Vo=0.5V or 4.5V VDD=10V, Vo=1.0V or 9.0V LOW Level Input Voltage VIL VDD=15V, Vo=1.5V or 13.5V VDD=5V, Vo=0.5V or 4.5V VDD=10V, Vo=1.0V or 9.0V HIGH Level Input Voltage VIH VDD=15V, Vo=1.5V or 13.5V VDD=5V, Vo=0.4V LOW Level Output Current (Note IOL VDD=10V, Vo=0.5V 3) VDD=15V, Vo=1.5V VDD=5V, Vo=2.5V HIGH Level Output Current (Note IOH VDD=10V, Vo=9.5V 3) VDD=15V, Vo=13.5V VDD=15V, VIN=0V Input Current IIN VDD=15V, VIN=15V Note 3: IOH and IOL are tested one output at a time. PARAMETER SYMBOL MIN TYP 0.005 0.010 0.015 0 0 0 5 10 15 2 4 6 3 6 9 3.6 9.0 34.0 130 8.0 30.0 -5 -10 -5 10 MAX 20 40 80 0.05 0.05 0.05 UNIT A
V
4.95 9.95 14.95
V 1.5 3.0 4.0
V
3.5 7.0 11.0 1.96 2.66 10.4 4.27 2.25 8.8
V
mA
mA -0.3 0.3 A
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UTC CD4541
AC ELECTRICAL CHARACTERISTICS
(Note 4, Ta=25 , CL=50pF (refer to test circuits)) PARAMETER Output Rise Time SYMBOL tTLH TEST CONDITIONS VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V Any Input MIN TYP 50 30 25 50 30 25 1.8 0.6 0.4 3.2 1.5 1.0 200 100 70 2.5 6.0 8.5 170 75 50 5.0 100
CMOS IC
Output Fall Time Turn-Off, Turn-On Propagation Delay, Clock to Q (28 Output) Turn-On, Turn-Off Propagation Delay, Clock to Q (216 Output) Clock Pulse Width
tTHL
tPLH, tPHL
tPHL, tPLH
MAX 200 100 80 200 100 80 4.0 1.5 1.0 8.0 3.0 2.0
UNIT ns
ns
s
s
tWH(CL)
400 200 150
ns 1.0 3.0 4.0
Clock Pulse Frequency
fCL
MHz
MR Pulse Width
tWH(R)
400 200 150
ns 7.5 pF pF
Average Input Capacitance CI Power Dissipation Capacitance CPD (Note 5) Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: CPD determines the no load AC power consumption of any CMOS device.
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OPERATING CHARACTERISTICS
CMOS IC
With Auto Reset pin set to a "0" the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a "1". Both types of reset will result in synchronously resetting all counter stages independent of counter state. The RC oscillator frequency is determined by the external RC network, i.e.:
f=
1 if (1 kHz 2.3 RtcCtc
f
100kHz)
and RS ~ 2 Rtc where RS 10 k 8 10 13 The time select inputs (A and B) provide a two-bit address to output any one of four counter stages (2 , 2 , 2 , 16 n and 2 ). The 2 counts as shown in the Division Ratio Table represent the Q output of the Nth stage of the counter. When A is "1", 216 is selected for both states of B. However, when B is "0", normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 28). The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition and Q/Q select pin is set to a "0" the Q output is a "0". Correspondingly, when Q/Q select pin is set to a "1" the Q output is a "1". When the mode control pin is set to a "1", the selected count is continually transmitted to the output. But, with mode pin "0" and after a reset condition the RS flip-flop resets (see Logic Diagram), counting commences and after 2n-1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2n-1 counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation.
RC Oscillator Frequency as a Function of RTC and C 1.0M
RC Oscillator Frequency as a Function of RTC and C 70
DSCILLATOR FREQUENCY,f (kHz)
100 k
DSCILLATOR FREQUENCY,f (kHz)
VDD =10V
VDD =10V
7
10k
0.7
1.0k 0.0001 0.001 0.01 ) 0.1 RESISTANCE , RTC ( K
0.07
1.0k
10k
100k
1.0M
CAPACITANCE, C(F) f as a function of RTC and (C=100pF, Rs=2RTC)
f as a function of C and (RTC =56 K , Rs =120k )
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UTC CD4541
Oscillator Circuit Using RC Configuration 3 TO CLOCK CIRCUIT INTERNAL RESET 2 RS CTC RTC 1
CMOS IC
TEST CIRCUIT AND WAVEFORMS
P o w e r D is s ip a tio n T e s t C ir c u it a n d W a v e fo r m s
V DD
PU LSE GENERATOR
Rs AR Q /Q S E L E C T MODE A B MR V SS Q CL
( R t c a n d C tc o u tp u ts a r e le ft o p e n )
tW H 20 ns 90% Rs 50% 10%
(C L )
20 ns
50% D U TY C YC LE
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S w itc h in g T im e T e s t C irc u it a n d W a v e fo rm s
VDD
CMOS IC
PU LS E GENERATOR
Rs AR Q /Q S E L E C T MODE A B MR V SS Q CL
tW H 20 ns 90% Rs 50% 10%
(C L )
20 ns
50%
tP L H
tP H L 90%
50% Q 10% tT L H
50%
tT H L
UTC assum es no responsibility for equipm ent failures that result from using products at v alues that exceed, ev en m om entarily, rated v alues (such as m axim um ratings, operating condition ranges, or other param eters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, dev ices or system s where m alfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The inform ation presented in this docum ent does not form part of any quotation or contract, is believ ed to be accurate and reliable and m ay be changed without notice.
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CO., LTD.
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